This invention relates generally to methods and apparatus for implementing Maximum Transition Run (MTR) coding schemes, and to corresponding decoding systems.
Channel codes, whereby input data bits are mapped to channel bits by a coding process, are commonly used to improve the characteristics of the bit-stream supplied to a recording channel. The code rate for such a code is usually specified as M/N and indicates the ratio of the number of data bits M to channel bits N. MTR codes are a particular type of channel code used to improve the characteristics of data to be supplied to a magnetic recording channel wherein the data is recorded on a magnetic recording medium such as a magnetic disk or tape. With air MTR codes the number of consecutive transitions that can occur in the magnetization pattern on the recording medium is limited to a particular number denoted by xe2x80x9cjxe2x80x9d. Thus, when used in conjunction with the NRZI (Non-Return-to-Zero-Inversion) recording format where xe2x80x9c1xe2x80x9d represents a magnetic transition and xe2x80x9c0xe2x80x9d no transition, an MTR code limits the maximum number of consecutive 1""s at the NRZI encoder input. This j constraint has the desirable consequence of reducing errors in data recovery. More particularly, the bit-error rate performance is improved by providing a distance gain, i.e. an increase in the minimum Euclidean distance between recording patterns, or by eliminating likely error events, thus reducing the likelihood of errors in sequence detectors on the data recovery side. For example, when used in conjunction with higher-order partial response shaping and maximum likelihood sequence detection such as in an E2PR4 partial response channel, MTR codes with j=2 can deliver a distance gain of 2.2 dB. MTR codes with j=2 are also write-friendly, allowing user data to be written to a disk at very high data rates. High code-rate MTR codes are therefore of great interest, and particularly so for the higher-order partial response channels used in disk drives for example. Particular examples of MTR codes and encoding/decoding systems are disclosed in European patent application no. 99113399.2, assigned to the Assignee of the present application, and the prior art discussed in the introduction thereof.
Run Length Limited (RLL) codes are another type of channel code commonly used in magnetic recording. These codes impose a (G, I) constraint on the recorded data sequence, where xe2x80x9cGxe2x80x9d denotes the maximum number of consecutive 0""s in the bit stream and xe2x80x9c1xe2x80x9d denotes the maximum number of consecutive 0""s in the odd and even interleaved bit streams. IEEE Transactions on Magnetics, vol. 34, pp. 2382-2386, July 1998, xe2x80x9cA New Target Response with Parity Coding for High Density Magnetic Recording Channelsxe2x80x9d, proposes a parity-based coding scheme in which a single parity bit is appended to RLL encoded data to allow detection of the dominant error events for a particular detector target. The proposed detection system is based on a Viterbi detector matched to the channel response which outputs estimates of the recorded code words, and a post-processor which correlates noise estimates with the dominant error events to indicate the type and position of the most-likely error event where the parity constraint is violated by an estimated code word.
As discussed further below, particular decoder systems embodying the present invention employ Noise Predictive Maximum Likelihood (NPML) detectors in conjunction with parity-based post processors. NPML, or xe2x80x9cfractional targetxe2x80x9d, detection with finite impulse response (FIR) or infinite impulse response (IIR) targets is disclosed in International patent applications no""s. WO 97/11544 and WO 98/52330 respectively, both assigned to the Assignee of the present application. Further, noise predictive post-processor designs for RLL encoded data are disclosed in the following: U.S. Pat. No. 5,949,831; International patent application no. PCT/US99/19910; and U.S. patent application Ser. No. 09/517,352, all assigned to the Assignee of the present application. In these cases, the post-processing schemes utilize IIR prediction/whitening filters and the error event detection mechanism is threshold based. Also as discussed below, particular encoder systems embodying the invention utilize a partial response precoder which operates on parity-coded data. U.S. Pat. No. 5,809,081 discloses systems in which an encoder adds one or two bits to an input word to generate a code string for supply to a precoder such that the precoded string has a preselected parity structure. U.S. Pat. No. 5,809,080 discloses a noise predictive Viterbi detector for such a system, the detector using a combined encoder parity and partial response trellis.
According to a first aspect of the present invention there is provided a method for encoding a succession of M-bit data words to produce a succession of N-bit code words, where N greater than M, for supply to a magnetic recording channel, the method comprising the steps of:
encoding each M-bit data word in accordance with an MTR coding scheme to produce a G-bit word, where N greater than G greater than M, such that the maximum number of consecutive bits of a first value in a succession of said G-bit words is limited to a first predetermined value j1; and encoding said G-bit word to produce a said N-bit word in accordance with a second coding scheme wherein at least one parity bit, dependent on the bit-values of said G-bit word, is generated, such that the N-bit word satisfies a predetermined parity condition, and wherein bits of said first value in the G-bit word are mapped to respective bits of the N-bit word which are each of different value to the immediately preceding bit in the N-bit word;
wherein the second coding scheme is such that, in a succession of said N-bit words, the maximum number of consecutive bits which are each of different value to the immediately preceding bit is limited to a second predetermined value j2.
In methods embodying the present invention, therefore, M-bit data words are first encoded according to an MTR encoding scheme to produce G-bit words satisfying an MTR j=j1 constraint. Thus, in a succession of these G-bit words, the maximum number of consecutive bits of a first value (which value corresponds to a transition in the eventual channel magnetization pattern) is limited to j1. (As will be appreciated, in embodiments conforming to the convention for MTR codes, the said bits of a first value will be bits of value xe2x80x9c1xe2x80x9d). Each G-bit word is then encoded to produce an N-bit word in accordance with a second coding scheme wherein one or more parity bits is generated, and bits of said first value in the G-bit word are mapped to respective bits of the N-bit word which are each of a different value to the immediately preceding bit of the N-bit word. Thus, bits of said first value are effectively mapped to bit-value transitions in the N-bit words, and hence to transitions in the magnetization pattern corresponding to the N-bit code words which is obtained on recording. The second coding scheme is implemented such that the maximum number of consecutive bit-value transitions in the output N-bit code words is limited to a predetermined value j2. The second coding scheme therefore results in a succession of N-bit words which satisfy an MTR j=j2 constraint as well as a predetermined parity condition. Thus, in contrast to mere appending of a single parity bit to an RLL code as in the prior proposal referenced above, in embodiments of the present invention an MTR coding scheme is employed in the first encoding stage, and the second encoding stage, which involves the parity coding, is performed in such a manner that the resulting N-bit word still satisfies an MTR j constraint. As will be demonstrated by the particular examples described below, such encoding methods allow substantial performance gains to be achieved over both conventional MTR codes and RLL codes combined with a single parity bit. Moreover, while in general one or more parity bits may be employed, preferred embodiments utilize a plurality of parity bits. This provides for significantly improved operation by reducing the likelihood of errors on the data recovery side, while still preserving the MTR j constraint in the output code words on the recording side. Thus, the parity condition imposed on the output code words may be defined by one or more equations depending on the particular number of parity bits employed.
While the parity coding and the mapping of bits to bit-value transitions in the output code words could be combined in a single coding step, to simplify the encoding process it is preferred that the mapping of bits to bit-value transitions is performed as a separate step to the parity coding. In particular, the mapping process is most conveniently implemented by a partial response preceding step, specifically a 1/(1⊕D) coding step. Further, while the 1/(1⊕D) coding step could be performed before the parity coding step, the encoding process is simplified in preferred embodiments by performing the parity coding step before the 1/(1⊕D) coding step. Either way, it will be appreciated that, as a result of the parity coding (and any further coding steps as discussed below), not all of the bits of said first value in a G-bit word may map directly to bit-value transitions in the resulting N-bit code word, and references to this mapping process herein should be construed accordingly.
In some embodiments, the second encoding scheme may consist simply of a parity coding step, whereby the one or more parity bit(s) are generated and inserted in the G-bit word, followed by a 1/(1⊕D) coding step whereby the resulting parity-coded word is subjected to 1/(1⊕D) coding to produce the required N-bit code word. In other embodiments, the second encoding scheme may include one or more further encoding steps, and the order of the various steps can be varied in these embodiments. In general therefore, the parity bits generated in accordance with the second encoding scheme may be dependent directly or indirectly on the bit-values of the initial G-bit word, and may be inserted in the G-bit word itself or a word resulting from further encoding the G-bit word before the parity coding is performed, depending on the number and order of steps in the process of encoding a G-bit word into an N-bit word. The important point is that an MTR j constraint is preserved in the output N-bit words. The way in which this is achieved will in general depend on the particular MTR coding scheme employed in the first encoding stage. For example, the (or each) parity bit may be inserted between a predetermined pair of bits in the G-bit word, the parity bit locations being selected such that the resulting code word satisfies the required MTR constraint. In other embodiments, additional encoding steps may be employed as already mentioned. In preferred embodiments, the second encoding scheme is designed such that j2=j1. However, even with careful selection of the parity-bit location(s), the parity coding will usually result in a less stringent j constraint in the parity-coded word. Accordingly, in particularly preferred embodiments the parity-coded word is further encoded in accordance with a further coding scheme, such as an appropriately designed block code, to improve the MTR j constraint in the resulting N-bit words. For example, in a particular embodiment discussed below where the parity coding alone would result in j2 greater than j1, such a block code is employed to restore j2 to j1. In another embodiment discussed below where the initial MTR coding scheme results in a time-varying j=3/4 constraint, the second encoding scheme is efficiently designed such that the parity coding alone would result in j2=j1=4 (or more precisely 3/4), but with runs of four consecutive transitions occurring more frequently in the output code words. Here, a block code is employed to improve the output MTR j constraint by reducing the frequency of occurrence of four consecutive transitions. In general therefore, the purpose of the block code (or other further coding scheme) in preferred embodiments is to eliminate at least some occurrences of the maximum number of consecutive bit value transitions in the set of possible N-bit code words, the block code being designed such that j2=j1. As in the examples below, in particularly preferred embodiments the block code employed as the further coding scheme is a rate X/X block code, where Xxe2x89xa6N, to avoid reduction of the overall code rate as far as possible.
The MTR coding scheme used in the initial step of encoding an M-bit word into a G-bit word may take various forms depending on the particular MTR code (or codes) used. For example, in some embodiments a basic rate M/G MTR code may be applied so that the MTR coding scheme consists simply of a single application of the rate M/G MTR code. In other embodiments, for example, a basic MTR code may be applied to portions of the input M-bit word, sequentially or in parallel, so that the resulting MTR-coded portions collectively constitute the G-bit word. In particular, in preferred embodiments the step of encoding each M-bit data word comprises partitioning the M-bit data word into a plurality of m-bit blocks and encoding each m-bit block in accordance with a rate m/g MTR code to produce a g-bit block, whereby the resulting plurality of g-bit blocks produced from the M-bit data word collectively constitute the G-bit word.
Particular examples of encoding methods which employ the above ideas to achieve highly efficient, high code-rate systems will be described in detail below. However, those skilled in the art will be able to design other examples based on the techniques described herein.
A second aspect of the present invention provides a method for processing data reproduced from a magnetic recording medium, wherein the reproduced data corresponds to a succession of N-bit code words, produced from a succession of M-bit data words by an encoding method according to the first aspect of the invention, recorded on the recording medium. The processing method comprises the steps of:
processing the reproduced data in dependence on said predetermined parity condition to detect the N-bit code words corresponding thereto;
decoding each N-bit code word in accordance with a decoding scheme which is the inverse of said second encoding scheme to produce the corresponding said G-bit word; and
decoding each G-bit word in accordance with an MTR decoding scheme which is the inverse of said MTR encoding scheme to recover the corresponding said M-bit data word.
It is to be appreciated that, in general, where features are described herein with reference to a method embodying the invention, corresponding features may be provided in accordance with apparatus embodying the invention, and vice versa. For example, a third aspect of the present invention provides apparatus for encoding a succession of M-bit data words to produce a succession of N-bit code words, where N greater than M, for supply to a magnetic recording channel, the apparatus comprising:
a first encoder for encoding each M-bit data word in accordance with an MTR coding scheme to produce a G-bit word, where N greater than G greater than M, such that the maximum number of consecutive bits of a first value in a succession of said G-bit words is limited to a first predetermined value j1; and
a second encoder for encoding said G-bit word to produce a said N-bit word in accordance with a second coding scheme whereby the second encoder generates at least one parity bit, dependent on the bit-values of said G-bit word, such that the N-bit word satisfies a predetermined parity condition, and maps bits of said first value in the G-bit word to respective bits of the N-bit word which are each of different value to the immediately preceding bit in the N-bit word;
wherein the second coding scheme is such that, in a succession of said N-bit words, the maximum number of consecutive bits which are each of different value to the immediately preceding bit is limited to a second predetermined value j2.
A fourth aspect of the invention provides apparatus for processing data reproduced from a magnetic recording medium, wherein the reproduced data corresponds to a succession of N-bit code words, produced from a succession of M-bit data words by encoding apparatus according to the third aspect of the invention, recorded on said recording medium. The processing apparatus comprises:
a detector for processing the reproduced data in dependence on said predetermined parity condition to detect the N-bit code words corresponding thereto;
a first decoder for decoding each N-bit code word in accordance with a decoding scheme which is the inverse of said second encoding scheme to produce the corresponding said G-bit word; and
a second decoder for decoding each G-bit word in accordance with an MTR decoding scheme which is the inverse of said MTR encoding scheme to recover the corresponding said M-bit data word.
A further aspect of the invention provides a data storage system comprising: encoder apparatus according to the third aspect of the invention; a recording channel comprising means for recording a succession of the N-bit code words on a magnetic recording medium, and means for reading the magnetic recording medium to generate reproduced data corresponding to said N-bit code words; and processing apparatus according to the fourth aspect of the invention.